中圖分類號(hào)： TN402 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.200858 中文引用格式： 王婷，陳斌岳，張福海. 基于FPGA的卷積神經(jīng)網(wǎng)絡(luò)并行加速器設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2021，47(2)：81-84. 英文引用格式： Wang Ting，Chen Binyue，Zhang Fuhai. Parallel accelerator design for convolutional neural networks based on FPGA[J]. Application of Electronic Technique，2021，47(2)：81-84.
Parallel accelerator design for convolutional neural networks based on FPGA
Wang Ting，Chen Binyue，Zhang Fuhai
College of Electronic Information and Optical Engineering，Nankai University，Tianjin 300350，China
Abstract： In recent years, convolutional neural network plays an increasingly important role in many fields. However, power consumption and speed are the main factors limiting its application. In order to overcome its limitations, a convolutional neural network parallel accelerator based on FPGA platform is designed. Ultra96-v2 is used as the experimental development platform, and the design and implementation of convolutional neural network computing IP core adopts advanced design synthesis tools. The design and implementation of convolutional neural network accelerator system based on FPGA is completed by using vivado development tools. By comparing the recognition rate of GPU and CPU, the convolutional neural network based on FPGA optimized design takes much less time to process a picture than CPU, and reduces the power consumption of GPU by more than 30 times. It shows the performance and power consumption advantages of FPGA accelerator design, and verifies the effectiveness of this method.
Key words : parallel computing；convolutional neural network；accelerator；pipeline
