摘要： 为了满足对于集成电路的复杂设计需求，继承了C++扩展库的SystemC的开发与设计应运而生。SytemC可以满足对于软硬件协同设计的要求，在设计的过程中，可以进行快速仿真和验证。针对于通信协议(ISO/IEC 18000-6C)进行较高层次的建模设计，采用函数调用的方式实现询问机和标签之间的协议通信。针对于UHF RFID(Ultra High Frequency Radio Frequency Identification)通信协议，从系统级设计到行为级设计，实现该协议的自顶向下的设计，完成了标签识别层和基带通信链路层的设计。最后采用Vivado HLS综合软件将SystemC源代码转化成Verilog等硬件描述语言，软件描述的系统级综合成RTL级代码。针对标签基带链路ENCODE_T模块，在Microsoft Visual C++ 6.0中对数据“1001001001011001”进行fm0\miller编码仿真之后，在Modelsim中完成了波形验证，并通过Vivado HLS综合软件将其转化为RTL级电路。
中圖分類號(hào)： TN402 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.201117 中文引用格式： 戚皖青，卜剛，李姝萱. 基于SystemC語(yǔ)言實(shí)現(xiàn)UHF RFID系統(tǒng)自頂向下設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2021，47(5)：45-49. 英文引用格式： Qi Wanqing，Bu Gang，Li Shuxuan. Top down design of UHF RFID tag based on SystemC[J]. Application of Electronic Technique，2021，47(5)：45-49.
Top down design of UHF RFID tag based on SystemC
Qi Wanqing，Bu Gang，Li Shuxuan
School of Electronic Information Engineering，Nanjing University of Aeronautics and Astronautics，Nanjing 211106，China
Abstract： With the development of science and technology, the design of integrated circuit becomes more and more complex.In the design process, the division of hardware and software also produces more choices. In order to meet the complex design requirements for integrated circuits, the development and design of SystemC, which inherits the C + + extension library, came into being. SytemC can meet the requirements of hardware and software codesign, and can be quickly simulated and verified in the design process. In this paper, the communication protocol(ISO/IEC 18000-6C) is modeled and designed at a higher level. The protocol communication between interrogator and tag is realized by function call. For UHF RFID(Ultra High Frequency Radio Frequency Identification)communication protocol, from system level design to behavior level design, the top-down design of the protocol is realized, and the design of tag identification layer and baseband communication link layer is completed. Finally, the source code of this systemc is transformed into Verilog and other hardware description languages by using Vivado HLS synthesis software, and the software description of system level is synthesized into RTL code. This paper focuses on label baseband link encode_T module, after FM0 / Miller coding simulation of data "1001001001011001" in Microsoft Visual C++ 6.0, the waveform verification is completed in Modelsim, and it is transformed into RTL level circuit by Vivado HLS integrated software.
Key words : software and hardware；collaborative design；high level；protocol communication；top-down
0 引言
隨著科技的發(fā)展，集成電路的規(guī)模變得龐大和復(fù)雜，電子系統(tǒng)設(shè)計(jì)(Electronic System Level，ESL)流程是目前最先進(jìn)片上系統(tǒng)設(shè)計(jì)流程方法。
