《電子技術(shù)應(yīng)用》
您所在的位置:首頁 > 嵌入式技术 > 设计应用 > 基于FPGA的LVDS多通道视频流自动校准设计与实现
基于FPGA的LVDS多通道视频流自动校准设计与实现
电子技术应用
陈宁1,谯谊1,雷伟林2,杜柏峰2,赵阳生2
1.利亚德集团 智能显示研究院;2.中国石油大学(北京) 信息科学与工程学院/人工智能学院
摘要: 基于Micro-LED产品系列,设计了一种基于FPGA的LVDS自动校准多通道视频流传输系统。系统平台外挂GSV2011解码芯片,把解码得到的2K@120 Hz/4K@60 Hz视频流信号,通过自定义封装为80 bit数据推送到LYDNT27001恒流源显示驱动芯片。系统中视频流数据传输涉及多级FPGA芯片数据传输,使用LVDS低压差分传输技术,在数据流传输过程中找到参考端和监视端信号,从而去调节SerDes中数据位对齐和采样稳定性的问题。该系统视频流数据通过LVDS多通道传输,传输速率可达10 Gb/s。此试验工程表明,该系统能够稳定、可靠、高效工作,具备一定的工程实用价值。
關(guān)鍵詞: FPGA LVDS SerDes micro-LED 自动校准
中圖分類號(hào):TP274 文獻(xiàn)標(biāo)志碼:A DOI: 10.16157/j.issn.0258-7998.244839
中文引用格式: 陳寧,譙誼,雷偉林,等. 基于FPGA的LVDS多通道視頻流自動(dòng)校準(zhǔn)設(shè)計(jì)與實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用,2024,50(6):84-88.
英文引用格式: Chen Ning,Qiao Yi,Lei Weilin,et al. Design and implementation of automatic calibration with LVDS multi-channel video stream based on FPGA[J]. Application of Electronic Technique,2024,50(6):84-88.
Design and implementation of automatic calibration with LVDS multi-channel video stream based on FPGA
Chen Ning1,Qiao Yi1,Lei Weilin2,Du Baifeng2,Zhao Yangsheng2
1.Leyard Group, Intelligent Display Research Institute;2.School of Information Science and Engineering / School of Artificial Intelligence, China University of Petroleum (Beijing)
Abstract: Based on the Micro-LED product series, this experimental project has designed an FPGA-based LVDS automatic calibration for the multi-channel video stream transmission system. The system platform is equipped with an external GSV2011 decoding chip, which converts the obtained 2K@120 Hz/4K@60 Hz video stream signals into 80-bit data package according to custom specifications, and then pushes them to the LYDNT27001 constant current source display driver chip. In thise system, the video stream data transmission involves multiple levels of FPGA chip data transfer, utilizing LVDS low-voltage differential transmission technology. In order to adjust the data bit alignment and sampling stability issues with the SerDes, the reference and monitor signals are identified during the process of data stream transmission video stream data of this system transmits through LVDS multiple channels, which can achieve a transmission rate of up to 10 Gb/s. This experimental project demonstrates that the system can operate stably, reliably, and efficiently, therefore it has certain practical value in engineering field.
Key words : FPGA;LVDS;SerDes;Micro-LED;automatic calibration

引言

隨著信息時(shí)代的蓬勃發(fā)展,顯示行業(yè)需求的提高,主流顯示技術(shù)QLED、MiniLED、OLED,逐漸被新一代Micro-LED微顯示器技術(shù)所取代。Micro-LED具有高分辨率、高色域、高穩(wěn)定性、低功耗、尺寸小、壽命長(zhǎng)等諸多優(yōu)點(diǎn),已成為工業(yè)界研究的熱點(diǎn)[1-3]。市場(chǎng)上Micro-LED恒流源驅(qū)動(dòng)芯片能夠搭載高分辨率的視頻流數(shù)據(jù)。這意味著視頻流傳輸需要更大的帶寬,更高的傳輸速率。

在高速通信領(lǐng)域中一般采用串行/解串器SerDes技術(shù)去做多通道并行通信,SerDes處理信號(hào)走LVDS差分端口。通過LVDS低壓差分技術(shù)傳輸信號(hào),LVDS比傳統(tǒng)接口有較低的電壓擺幅,較強(qiáng)的抗干擾能力,較高的傳輸速率等優(yōu)點(diǎn)[4]。由于是高速傳輸,時(shí)鐘的采樣具有不穩(wěn)定性和數(shù)據(jù)位對(duì)齊等問題。傳統(tǒng)的處理方法是通過在PC編寫軟件對(duì)采集的數(shù)據(jù)進(jìn)行比較,從而確保通道采樣的正確性[5],通過上位機(jī)采集,使得系統(tǒng)設(shè)計(jì)更為復(fù)雜,調(diào)節(jié)通道中數(shù)據(jù)位對(duì)齊需要一個(gè)個(gè)數(shù)據(jù)測(cè)試,時(shí)間較長(zhǎng)。隨著芯片技術(shù)的發(fā)展,現(xiàn)在高端FPGA芯片中具有GT收發(fā)器硬核資源,把數(shù)據(jù)和時(shí)鐘綁定在一起,通過特殊的編碼方案(例如8B/10B編碼方案)傳輸?shù)浇邮斩耍_保通道中數(shù)據(jù)的正確性[6-9],但是芯片成本較高,在工程應(yīng)用上浪費(fèi)資源。也有通過眼圖去觀察數(shù)據(jù)的采樣率,確保通道中數(shù)據(jù)能夠被正確接收[10]。本系統(tǒng)采用Xilinx FPGA xc7s15芯片,該芯片不具備GT收發(fā)器等資源。由于無法將時(shí)鐘和數(shù)據(jù)綁定到同一通道,因此在PCB硬件走線時(shí)會(huì)有差分時(shí)鐘線和差分?jǐn)?shù)據(jù)線。具體來說本系統(tǒng)設(shè)計(jì)方案主要體現(xiàn)在以下幾個(gè)方面:(1)通過Xilinx原語去把串行數(shù)據(jù)轉(zhuǎn)換為并行數(shù)據(jù),差分時(shí)鐘轉(zhuǎn)為單端時(shí)鐘,并且用單端時(shí)鐘去采樣通道數(shù)據(jù);(2)通過尋找參考端和監(jiān)視端自適應(yīng)去調(diào)節(jié)BITSLIP數(shù)據(jù)位對(duì)齊模塊和采樣穩(wěn)定性IDELAY模塊;(3)把采樣得到的數(shù)據(jù)推送到恒流源芯片中。本系統(tǒng)在節(jié)省芯片購買成本的同時(shí),保證了視頻流數(shù)據(jù)能夠高效、可靠、穩(wěn)定地傳輸,具備實(shí)際工程應(yīng)用價(jià)值。


本文詳細(xì)內(nèi)容請(qǐng)下載:

http://m.ihrv.cn/resource/share/2000006036


作者信息:

陳寧1,譙誼1,雷偉林2,杜柏峰2,趙陽生2

(1.利亞德集團(tuán) 智能顯示研究院,北京 100089;2.中國(guó)石油大學(xué)(北京) 信息科學(xué)與工程學(xué)院/人工智能學(xué)院,北京 102249)


Magazine.Subscription.jpg

此內(nèi)容為AET網(wǎng)站原創(chuàng),未經(jīng)授權(quán)禁止轉(zhuǎn)載。