中圖分類號： TN47
文獻(xiàn)標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.211460
中文引用格式： 徐波. 基于多相濾波的四路并行抽樣算法及實(shí)現(xiàn)[J].電子技術(shù)應(yīng)用，2021，47(11)：110-115.
英文引用格式： Xu Bo. The four parallel sampling algorithm based on polyphase filtering and its implementation[J]. Application of Electronic Technique，2021，47(11)：110-115.

The four parallel sampling algorithm based on polyphase filtering and its implementation

Abstract： In the development of a certain type of digital signal processing module, high-speed AD samples the RF signal, but the clock generation module cannot output the 320 MHz clock, which causes the high-speed AD to work normally at the sampling rate of 320 MS/s. Therefore, in a high-performance FPGA, the signal is first sampled 3 times, and the JESD204B IP core performs a 1:4 serial-to-parallel conversion on the high-speed signal. Finally, the serial-to-parallel conversion signal is subjected to polyphase filtering and down sampling. The article first introduces the background of the subject, then briefly describes the composition, function and performance indicators of the signal processing module, and deeply analyzes the problems existing in the sampling rate of 320 MS/s, and proposes four parallel sampling algorithm for the problem. Based on the algorithm, the system was modeled and simulated by MATLAB, and the simulation results were consistent with expectations. It selects Xilinx′s high-performance FPGA and combines the low-pass filter parameters in the system model to implement the circuit. Finally, the digital signal processing module and the software and hardware joint test environment of software tools such as Vivado are built to verify and give the experimental results.

Key words : polyphase filter；4-way parallel sampling algorithm；decimation