摘要： 在SIP（System In a Package）系统中集成具有LVDS（Low-Voltage Differential Signal）接口的多通道高速模数转换器（Analog-to-Digital Converter，ADC）时，面临不同LVDS输出通道延时不同所导致的数据采集错误的问题，为此设计了一个多通道自适应LVDS接收器。通过采用数据时钟恢复技术产生一个多相位的采样时钟，并结合ADC的测试模式来确认每一个通道的采样相位，能够自动对每一个通道的延时分别进行调整，以达到对齐各通道采样相位点，保证数据正确采集的目的。最后，基于先进CMOS工艺进行了接收器的设计、仿真、后端设计实现和流片测试，仿真和流片后的板级测试结果均表明该接收器能够对通道延迟进行自动调节以对齐采样相位，且最大的采样相位调节范围为±3 bit，信噪比大于65 dB，满足了设计要求和应用需求。
1.CETC Suntai Information Technology Co.，Ltd.； 2.No. 58 Research Institute， CETC
Abstract： When integrating multi-channel high-speed ADC (Analog-to-Digital Converter) with LVDS (Low Voltage Differential Signal) interface in SIP (System In a Package) system, it is faced with the problem of clock-to-data skew, data-to-data skew, accumulated clock jitter and so on caused by different LVDS channel with different delays. Therefore, a multi-channel LVDS receiver was designed in this paper which can adaptively adjust the skew of each LVDS channel. The receiver uses data clock recovery technology to generate eight multi-phase sampling clocks, combining with ADC test mode to confirm the sampling phase of each channel, the delay of each channel can be automatically adjusted, aiming to align the sampling phase of channels and ensure the data correct. Finally, the receiver was designed, simulated, and realized based on advanced CMOS technology. The results of simulation and chip test show that the receiver can automatically adjust the delay of each channel to align the sampling phase, the maximum range of sampling phase adjustment is ± 3 bit, and the signal-to-noise ratio is greater than 65 dB, which meets the design requirements and application requirements.
Key words : analog-to-digital converter（ADC）；multi-channels LVDS；phase locked loop；clock data recover
本文基于一個(gè)多通道信號(hào)處理系統(tǒng)的需求，選用了一款LVDS輸出接口、精度為16位的四通道ADC，其最高采樣速率可達(dá)125 MS/s。由于通道數(shù)目多，采用SIP（System In a Package）封裝后，LVDS各通道之間的時(shí)序誤差比較嚴(yán)重，尤其在高低溫環(huán)境下更是明顯，這些均加重了后續(xù)電路采樣時(shí)的設(shè)計(jì)難度，為此需要研究多通道LVDS的數(shù)據(jù)接收技術(shù)，確保系統(tǒng)正常接收ADC的數(shù)據(jù)。本文設(shè)計(jì)了一款基于先進(jìn)CMOS工藝的多通道LVDS接收單元，以便集成入SoC（System on Chip），實(shí)現(xiàn)處理器對(duì)ADC數(shù)據(jù)的讀取和處理。
